This invention relates to output buffer circuits for semiconductor integrated circuit devices, and more particularly to CMOS circuits for driving an output bus using low-voltage supplies.
When the transistor sizes used in integrated circuit devices are scaled to smaller dimensions to allow larger numbers of the devices to be constructed on a chip, it is preferable to lower the voltages used to supply the chip to reduce degradation caused by so-called "hot electron" effects. Further, the power dissipation and the switching speed in integrated circuit devices can be reduced by operating the devices at lower voltages. MOS integrated circuit devices such as microprocessor and memory circuits have for many years operated with +5 V power supplies, but currently many devices are being designed to operate with lower voltage supplies, such as +3.3 V. The lower supply voltage reduces hot electron effects and also reduces the power dissipation in each transistor. This lower power dissipation becomes quite important when hundreds of thousands of transistors are included on a single chip. In addition, the switching speed is reduced because the voltage swing between one logic level and the other is less.
Even though some recently-designed MOS integrated circuit devices are able to operate at these lower supply voltages, there are many MOS and bipolar devices which still use the traditional +5 V supplies. Particularly, almost all memory devices currently available are manufactured for use with +5 V supplies, and so a microprocessor device using a +3.3 V supply must be able to operate on a bus with these +5 V memory devices. Preferably, devices of each type of supply voltage should be able to share the same busses, without requiring separate interface circuits. A microprocessor chip using low-voltage supplies should be able to directly interface with memory chips using high-voltage supplies. Input protection devices commonly employed at all input pads of an MOS chip allow overvoltage without harm, so a low-voltage chip can accept higher-voltage logic levels at its input. Likewise, the inputs pads of a higher-voltage chip are usually specified to accept TTL logic levels, which are lower than the 5 V MOS levels, and so the low-voltage outputs can readily drive the inputs of the higher-voltage chip. A problem can arise, however, at the output terminals of the low-voltage chip; when several drivers are connected to a bus, as is the case for a main system bus of a microprocessor system, for example, and when some of the drivers are on low voltage chips while others are on higher-voltage chips, the situation of a higher voltage being present on the bus while the outputs of the low-voltage chip are tri-stated results in the possibility that the higher voltage on the bus will sink current into the lower-voltage power supply through the pull-up transistors of the output buffers of the low-voltage chip. Since there are perhaps thirty-two or sixty-four of these output buffers driving a system bus from a microprocessor chip, the current overload caused by this effect could be catastrophic, both for the +5 V driving chip and the +3.3 V receiving chip. Previously, this current sinking effect has been avoided by stacking two transistors instead of one pull-up transistor, but this has needlessly increased the chip size; the output buffer generally employs the largest transistor sizes on a typical chip, and since there are perhaps thirty-two or sixty-four of these output buffers for the main data bus alone, the use of stacked transistors is not tolerable.
Even if a +3.3 V CMOS output buffer is driving only a single-source bus, i.e., point-to-point, the bus can be driven to above +3.3 V by the receiver's input circuitry or by other means, and so the improved circuit of the invention is useful in such a situation as well.
Thus it would be desirable to provide an improved way of interfacing integrated circuit devices employing low-voltage logic levels (and thus low-voltage power supplies) with other chips using higher-voltage logic levels. It would also be desirable to provide an improved output buffer circuit using a low-voltage supply, wherein the circuit will tolerate overvoltage on its output node without sinking current from the output node into the power supply of the circuit. In addition, it would be desirable to provide an improved, smaller-sized (thus lower-cost and lower-power) output buffer circuit for use in interfacing to higher voltage logic levels.